Conventional metrology methods are based on dedicated metrology structures or targets. In semiconductor manufacture and patterning processes in particular, process control is enabled by performing metrology on specific dedicated structures, either in the scribe lines between dies or within the die itself. Metrology methods face the challenges of reflecting the status of the actual device features accurately. The challenges are reflected in the ITRS 2011 guidelines under metrology difficult challenges—Measurement test structures and reference materials as following: “The area available for test structures is being reduced especially in the scribe lines. Measurements on test structures located in scribe lines may not correlate with in-die performance. Overlay and other test structures are sensitive to process variation, and test structure design must be improved to ensure correlation between measurements in the scribe line and on chip properties. Standards institutions need rapid access to state of the art development and manufacturing capability to fabricate relevant reference materials.”
The following documents are incorporated herein by reference in their entirety. U.S. Pat. No. 7,925,486 teaches creating a metrology target structure design for a reticle layout by simulating how one or more initial metrology target structures will be formed on a wafer based on one or more fabrication processes that will be used to form a metrology target structure on the wafer and one or more initial metrology target structure designs. The method also includes creating the metrology target structure design based on results of the simulating step. U.S. Pat. No. 7,631,286 teaches automatic generation of a metrology recipe without referencing a wafer, for locating measurement locations corresponding to test features on the wafer and directing the metrology tool to the locations, by calculating coordinates for the measurement locations based on mask data, lithography tool data, CAD data and process data. The metrology recipe directs the metrology tool to within 10 microns of test features formed on the wafer. Criteria may be input to a data base to identify multiple existing recipes and the automatically generated recipe may be generated to replace each identified recipe. U.S. Patent Publication No. 2003/0229410 teaches a metrology tool to measure a parameter of a semiconductor device that includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified as results from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations. U.S. Pat. No. 8,214,771 teaches scatterometry metrology target design optimization and is included herein by reference in its entirety.
Conventional metrology targets also must obey strict design rules in order to be compatible with specific metrology tool physical and software architecture. A known problem in the art is that despite the designer's intent, the complex process of design and insertion of metrology targets which themselves are becoming increasingly complex frequently results in design files which do not comply with design intent and in some cases even violate metrology design rules. These discrepancies arise due to the various processes the design files undergo subsequent to initial design and prior to final tape out for reticle manufacture. In many cases, layers are mislabeled, features rotated, offsets modified, features shrunk, features eliminated, features reproduced on the wrong design layer or lithographic polarity reversed, to mention just a few of the possible layout defects. Furthermore errors may also occur in the original design synthesis, such as incompatible pitches, duty cycles, and segmentation strategies. Furthermore, the set up parameters of the metrology tool such as acquisition coordinates, illumination and polarization are determined in the calibration phase with respect to the specific design values of each target where it is guided by the metrology recipe. Discrepancies from the design intent often result in a recipe that is inconsistent with design file thus encumber set up process and impact the quality of metrology measurements.